Method of manufacturing fan-out packaging device and fan-out packaging device manufactured thereby
AssigneeSilicon Box Pte. Ltd.
InventorSehat Sutardja
Life of this patent
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Abstract
Disclosed is a method of manufacturing a fan-out packaging device, which is a method of manufacturing a packaging device using a wafer or panel level packaging process, the method including forming a first dielectric layer having a first via hole on a fan-out packaging substrate, forming a redistribution layer (RDL) on the first dielectric layer and the first via hole, forming a second dielectric layer having a second via hole formed on the redistribution layer, and forming a bump structure on the second dielectric layer and the second via hole so as to be connected to the redistribution layer, wherein the redistribution layer includes a metal sealing ring to extend a conductor path in a plating process.
Claims28
A method of manufacturing a fan-out packaging device, which is a method of manufacturing a packaging device using a wafer or panel level packaging process, the method comprising:
- forming a first dielectric layer having a first via hole on a fan-out packaging substrate;
- forming a redistribution layer (RDL) on the first dielectric layer and the first via hole;
- forming a second dielectric layer having a second via hole formed on the redistribution layer;
- and
- forming a bump structure on the second dielectric layer and the second via hole so as to be connected to the redistribution layer, wherein
- the redistribution layer comprises a metal sealing ring to extend a conductor path in a plating process.
A fan-out packaging device, which is a packaging device using a wafer or panel level packaging process, the fan-out packaging device comprising:
- a fan-out packaging substrate;
- a first dielectric layer formed on the fan-out packaging substrate, the first dielectric layer comprising a first via hole formed by patterning, the first via hole being configured to expose a signal pad and a ground pad of a die;
- a redistribution layer (RDL) formed on the first dielectric layer and the first via hole;
- a second dielectric layer formed on the redistribution layer, the second dielectric layer comprising a second via hole formed by patterning, the second via hole being configured to expose a part of the redistribution layer;
- and
- a bump structure formed on the second dielectric layer and the second via hole, the bump structure being connected to the redistribution layer, wherein
- the redistribution layer comprises a metal sealing ring to extend a conductor path in a plating process.
Dependencies are inferred from the claim text.