Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsJihyun LEE, Kang Joon LEE, Seokwon LEE
Life of this patent
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Abstract
A semiconductor package including a first structure, a second structure, and an interconnect structure between the first structure and the second structure. The interconnect structure includes a first region extending from a center of the interconnect structure to a first distance, and a second region outside the first region. The interconnect structure includes a plurality of first connection members in the first region and a plurality of second connection members in the second region. The plurality of first connection members are arranged in a staggered form, and the plurality of second connection members are arranged in rows.
Claims20
A semiconductor package, comprising:
- a first structure;
- a second structure;
- and
- an interconnect structure between the first structure and the second structure,
- wherein the interconnect structure comprises
- a first region extending from a center of the interconnect structure to a first distance,
- a second region outside the first region, and
- a plurality of first connection members in the first region and a plurality of second connection members in the second region,
- the plurality of first connection members are arranged in a staggered form, and
- the plurality of second connection members are arranged in a row.
A semiconductor structure, comprising:
- a die base;
- and
- a connection structure on a surface of the die base,
- wherein the connection structure comprises
- a first region extending from a center of the connection structure to a first distance,
- a second region outside the first region,
- an insulating member including a plurality of through openings,
- a plurality of first connection pads in the first region, and
- a plurality of second connection pads in the second region,
- the plurality of first connection pads and the plurality of second connection pads are within respective ones of the plurality of through openings,
- the plurality of first connection pads are arranged in a staggered form, and
- the plurality of second connection pads are arranged in a row.
A semiconductor package, comprising:
- a substrate including a first die base, a plurality of first connection pads on an upper surface of the first die base, and a plurality of second connection pads on the upper surface of the first die base;
- a semiconductor structure including a second die base, a plurality of third connection pads on a lower surface of the second die base, and a plurality of fourth connection pads on the lower surface of the second die base;
- and
- an interconnect structure between the substrate and the semiconductor structure,
- wherein the interconnect structure comprises
- a first region extending from a center of the interconnect structure to a first distance,
- a second region outside the first region, and
- a plurality of first connection members in the first region and a plurality of second connection members in the second region,
- the plurality of first connection members are arranged in a staggered form, and
- the plurality of second connection members are arranged in a row.
Dependencies are inferred from the claim text.