Semiconductor chip and semiconductor package including the same

A semiconductor chip, comprising:

• a semiconductor substrate;
• a front connection pad on the semiconductor substrate;
• a lower protective insulating layer at least partially covering the semiconductor substrate and comprising a lower opening that exposes at least a portion of the front connection pad;
• an upper protective insulating layer comprising an upper opening communicatively coupled to the lower opening on the lower protective insulating layer, the upper protective insulating layer comprising an organic material;
• a lower cover insulating layer between the lower protective insulating layer and the upper protective insulating layer;
• a connection terminal coupled to the front connection pad through the lower opening and the upper opening and spaced apart from the upper protective insulating layer;
• and
• an upper cover insulating layer between the connection terminal and the upper protective insulating layer, the upper cover insulating layer comprising an inorganic material,
• wherein the connection terminal comprises:
• a pillar barrier layer contacting the upper cover insulating layer and the front connection pad;
• a conductive pillar comprising a pillar base layer on the pillar barrier layer;
• and
• a conductive cap on the conductive pillar.

A semiconductor package, comprising:

• a first semiconductor chip comprising:
• a first semiconductor substrate comprising a first active surface and a first inactive surface opposite to the first active surface;
• a wiring layer on the first active surface;
• a first front connection pad on the wiring layer;
• a first rear connection pad on the first inactive surface;
• a first through electrode electrically coupling the first front connection pad to the first rear connection pad;
• a lower protective insulating layer at least partially covering the wiring layer and comprising a lower opening that exposes at least a portion of the first front connection pad;
• an upper protective insulating layer comprising an upper opening communicatively coupled to the lower opening on the lower protective insulating layer, the upper protective insulating layer comprising an organic material;
• a lower cover insulating layer between the lower protective insulating layer and the upper protective insulating layer;
• and
• an upper cover insulating layer at least partially covering an upper surface and a side surface of the upper protective insulating layer and side surfaces of the lower protective insulating layer, the upper cover insulating layer comprising an inorganic material;
• a connection terminal coupled to the first front connection pad through the lower opening and the upper opening and spaced apart from the upper protective insulating layer, the upper cover insulating layer being disposed between the connection terminal and the upper protective insulating layer;
• a plurality of second semiconductor chips, each second semiconductor chip of the plurality of second semiconductor chips comprising:
• a second semiconductor substrate comprising a second active surface and a second inactive surface opposite to the second active surface;
• a second front connection pad on the second active surface;
• a second rear connection pad on the second inactive surface;
• and
• a second through electrode electrically coupling the second front connection pad to the second rear connection pad,
• wherein the plurality of second semiconductor chips are sequentially stacked on the first inactive surface of the first semiconductor chip;
• and
• an internal connection terminal coupling between the second front connection pad of a lowermost second semiconductor chip at a lowermost end from among the plurality of second semiconductor chips and the first rear connection pad, and coupling between the second front connection pad and the second rear connection pad of different second semiconductor chips from among the plurality of second semiconductor chips,
• wherein the connection terminal comprises:
• a pillar barrier layer contacting the upper cover insulating layer and the first front connection pad;
• a conductive pillar comprising a pillar base layer on the pillar barrier layer at least partially filling the lower opening and the upper opening;
• and
• a conductive cap on the conductive pillar.