Semiconductor package including a plurality of semiconductor chips

A semiconductor package comprising:

• a first substrate;
• a first semiconductor chip disposed on the first substrate;
• a bridge chip disposed on the first substrate and spaced apart from the first semiconductor chip;
• a second semiconductor chip disposed on a first region of the bridge chip and the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the bridge chip and the first semiconductor chip;
• and
• a conductive post disposed on a second region of the bridge chip and spaced apart from the second semiconductor chip,
• wherein the conductive post is electrically connected to the bridge chip.

A semiconductor package comprising:

• a first redistribution substrate;
• solder ball terminals disposed on a lower surface of the first redistribution substrate;
• a first semiconductor chip mounted on the first redistribution substrate and comprising a through-via;
• a bridge chip disposed on the first redistribution substrate and spaced apart from the first semiconductor chip, wherein the bridge chip has a first region and a second region;
• a second semiconductor chip disposed on the first semiconductor chip and the first region of the bridge chip, wherein the second semiconductor chip is electrically connected to the first semiconductor chip and the bridge chip;
• conductive posts disposed on the second region of the bridge chip and spaced apart from the first semiconductor chip;
• interconnection structures disposed on the first redistribution substrate and spaced apart from the bridge chip, the conductive posts, and the second semiconductor chip;
• a first molding layer disposed on the first redistribution substrate and covering the bridge chip, the first semiconductor chip, the second semiconductor chip, sidewalls of the conductive posts, and sidewalls of the interconnection structures;
• a second redistribution substrate disposed on the first molding layer and electrically connected to the conductive posts and the interconnection structures;
• an upper package disposed on the second redistribution substrate and vertically overlapping the conductive posts;
• and
• a heat dissipation structure disposed on the second redistribution substrate, and spaced apart from the semiconductor package, wherein the heat dissipation structure vertically overlaps the second semiconductor chip,
• wherein the second semiconductor chip is electrically connected to the upper package through the bridge chip, the conductive posts, and the second redistribution substrate,
• wherein the bridge chip comprises:
• a base substrate;
• a bridge insulating layer disposed on the base substrate;
• first connection pads disposed on an upper surface of the bridge insulating layer and electrically connected to chip pads of the second semiconductor chip;
• second connection pads disposed on the upper surface of the bridge insulating layer and spaced apart from the first connection pads;
• and
• connection structures disposed in the bridge insulating layer,
• wherein the first connection pads are respectively electrically connected to the second connection pads through the connection structures, and
• the conductive posts are respectively disposed on the second connection pads.