Semiconductor package with improved structural stability

A semiconductor package comprising:

• a first redistribution layer;
• a bridge chip on the first redistribution layer;
• a mold layer on the first redistribution layer, the mold layer enclosing the bridge chip;
• a second redistribution layer disposed on the mold layer;
• a conductive post extending through the mold layer vertically and connecting the first redistribution layer and the second redistribution layer;
• and
• a first semiconductor chip mounted on the second redistribution layer,
• wherein the first redistribution layer comprises:
• a substrate protection layer;
• a pad layer that includes a plurality of outer pads extending through the substrate protection layer vertically, a top surface of the substrate protection layer and a plurality of top surfaces of the plurality of outer pads being substantially flat and being coplanar with each other;
• an insulating pattern covering the substrate protection layer and the plurality of outer pads;
• and
• a plurality of interconnection patterns disposed on the insulating pattern,
• wherein each interconnection pattern of the plurality of interconnection patterns comprises:
• a head portion on a top surface of the insulating pattern;
• and
• a tail portion extended from a bottom surface of the head portion through the insulating pattern vertically and connected to the plurality of outer pads,
• wherein a total thickness variation (TTV) of the pad layer ranges from 0 μm to 10 μm.

A semiconductor package comprising:

• a first redistribution layer;
• a second redistribution layer disposed on the first redistribution layer;
• a bridge chip mounted on a bottom surface of the second redistribution layer;
• a mold layer enclosing the bridge chip, the mold layer between the first redistribution layer and the second redistribution layer;
• a conductive post extending through the mold layer vertically and connecting the first redistribution layer and the second redistribution layer;
• a first semiconductor chip mounted on a top surface of the second redistribution layer;
• and
• a chip stack including a plurality of second semiconductor chips that are vertically stacked on the top surface of the second redistribution layer and that are horizontally spaced apart from the first semiconductor chip,
• wherein the first redistribution layer comprises:
• a pad layer including a plurality of outer pads and a substrate protection layer that horizontally encloses the plurality of outer pads;
• an insulating pattern covering the plurality of outer pads and the substrate protection layer;
• and
• an interconnection pattern disposed on the insulating pattern, extending through the insulating pattern, and coupled to the plurality of outer pads,
• wherein a plurality of top surfaces of the plurality of outer pads are exposed to an outside of the substrate protection layer near a top surface of the substrate protection layer,
• wherein a top surface of the pad layer is substantially flat,
• wherein a plurality of bottom surfaces of the plurality of outer pads are exposed to the outside of the substrate protection layer near a bottom surface of the substrate protection layer, and
• wherein a bottom surface of the pad layer is uneven.