Surface treatment in integrated circuit package and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Shien Chen, Chi-Yen Lin, Po-Chen Chen, Wu-An Weng, Hsu-Hsien Chen
Life of this patent
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Abstract
A package includes a first integrated circuit die and a second integrated circuit die over and bonded to the first integrated circuit die. A first surface region of the second integrated circuit die is hydrophobic, and the first integrated circuit die and the second integrated circuit die are bonded together with dielectric-to-dielectric bonds and metal-to-metal bonds. The package further includes a first insulating material over the first integrated circuit and surrounding the second integrated circuit die. The first insulating material contacts the first surface region.
Claims20
A package comprising:
- a first integrated circuit die;
- a second integrated circuit die over and bonded to the first integrated circuit die, wherein a first surface region of the second integrated circuit die is hydrophobic, and wherein the first integrated circuit die and the second integrated circuit die are bonded together with dielectric-to-dielectric bonds and metal-to-metal bonds;
- and
- a first insulating material over the first integrated circuit die and surrounding the second integrated circuit die, wherein the first insulating material contacts the first surface region.
A package comprising:
- a first integrated circuit die;
- a first insulating material surrounding the first integrated circuit die;
- a second integrated circuit die over and bonded to the first integrated circuit die, wherein a first surface region of the second integrated circuit die comprises fluorine, wherein a fluorine concentration of the first surface region is at least 5 wt %;
- and
- a second insulating material over the first integrated circuit die and surrounding the second integrated circuit die, wherein the first surface region is disposed at an interface between the second insulating material and the second integrated circuit die.
A method comprising:
- etching a trench through an interconnect structure and extending into a semiconductor substrate, the trench being disposed in a scribe line region that is disposed between a first integrated circuit die and a second integrated circuit die;
- performing a surface treatment in the trench to form a first surface region in a first sidewall of the first integrated circuit die, wherein the first surface region is hydrophobic;
- depositing a protective layer over the first integrated circuit die and covering the trench;
- attaching a tape to a surface of the protective layer opposite to the first integrated circuit die;
- performing a backside planarization on a surface of the semiconductor substrate opposite to the tape;
- and
- after performing the backside planarization, removing the protective layer and the tape to fully separate the first integrated circuit die from the second integrated circuit die.
Dependencies are inferred from the claim text.