Stacked fet with bottom epi size control and wraparound backside contact

A method for fabrication of a semiconductor device, comprising:

• forming bottom active regions with a first semiconductor material through a shallow trench isolation region on a substrate, the bottom active regions including a faceted surfaces;
• filling regions between the bottom active regions with a second semiconductor material;
• recessing the second semiconductor material and the first semiconductor material to provide a level surface across the bottom active regions;
• laterally cutting the bottom active regions to provide a substantially uniform lateral dimension for each of the bottom active regions;
• forming a bottom interlevel dielectric layer (ILD);
• fabricating top structures including top active regions, gate structures and top metallization structures;
• removing the substrate from a bottom side;
• exposing the second semiconductor material on the bottom side of at least one of the bottom active regions;
• selectively removing the second semiconductor material to expose the faceted surfaces of the at least one of the bottom active regions;
• and
• forming a backside wraparound contact in contact with exposed surfaces including the faceted surfaces of the at least one of the bottom active regions.

A method for fabrication of a semiconductor device, comprising:

• forming sacrificial placeholders through a shallow trench isolation (STI) region formed on a substrate;
• epitaxially growing bottom active regions with a first semiconductor material from the sacrificial placeholders, the bottom active regions including top faceted surfaces and bottom faceted surfaces;
• filling regions between the bottom active regions with a second semiconductor material;
• recessing the second semiconductor material and the first semiconductor material to provide a level surface across the bottom active regions;
• forming an organic planarizing layer (OPL) over the level surface;
• etching through the OPL and portions of the bottom active regions to cut a substantially uniform lateral dimension into the bottom active regions;
• forming a bottom interlevel dielectric layer (ILD);
• fabricating top structures including top active regions, gate structures and top metallization structures;
• applying a carrier wafer over the top structures;
• flipping the semiconductor device;
• removing the substrate from a bottom side;
• exposing the second semiconductor material on the bottom side of at least one of the bottom active regions including removing exposed sacrificial placeholders and opening up the STI region;
• selectively removing the second semiconductor material to expose the bottom faceted surfaces of the at least one of the bottom active regions;
• and
• forming a backside wraparound contact in contact with exposed surfaces including the bottom faceted surfaces of the at least one of the bottom active regions.