Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package, comprising:

• a first redistribution wiring layer including a chip mounting region and a connector region that are spaced apart from each other, and the first redistribution wiring layer having first redistribution wirings;
• a plurality of first bonding pads and a plurality of second bonding pads provided on uppermost redistribution wirings of the first redistribution wirings at an upper surface of the first redistribution wiring layer, the plurality of first bonding pads disposed in the chip mounting region and the plurality of second bonding pads disposed in the connector region;
• at least one heat dissipation pad disposed in the chip mounting region at the upper surface of the first redistribution wiring layer;
• a semiconductor chip mounted in the chip mounting region on the first redistribution wiring layer such that a front surface on which chip pads are formed faces the first redistribution wiring layer, the semiconductor chip being in contact with the at least one heat dissipation pad;
• a molding member covering the semiconductor chip on the first redistribution wiring layer;
• a plurality of conductive through vias respectively penetrating the molding member and each conductive through via respectively disposed on a respective second bonding pad of the plurality of second bonding pads on the connector region;
• and
• a second redistribution wiring layer disposed on the molding member and having second redistribution wirings with each second redistribution wiring electrically connected to a respective conductive through via of the plurality of conductive through vias.

A semiconductor package, comprising:

• a first redistribution wiring layer including a chip mounting region and a connector region that are spaced apart from each other, and having first redistribution wirings;
• a plurality of first bonding pads and at least one heat dissipation pad respectively disposed in the chip mounting region on the first redistribution wiring layer, and a plurality of second bonding pads disposed in the connector region on the first redistribution wiring layer;
• a semiconductor chip mounted in the chip mounting region on the first redistribution wiring layer such that a front surface on which chip pads are formed faces the first redistribution wiring layer;
• a molding member covering the semiconductor chip on the first redistribution wiring layer;
• a plurality of conductive through vias each penetrating the molding member and respectively disposed on a respective second bonding pad of the plurality of second bonding pads in the connector region;
• and
• a second redistribution wiring layer disposed on the molding member and having second redistribution wirings with at least one electrically connected to a respective conductive through via of the plurality of conductive through vias,
• wherein the semiconductor chip includes a first heating zone configured to emit first heat and a second heating zone configured to emit second heat less than the first heat, and
• wherein at least one dummy chip pad among the chip pads is provided in the first heating zone and contacts the at least one heat dissipation pad.