Semiconductor package including a film substrate

A semiconductor package, comprising:

• a film substrate having a chip mounting area, and having an upper surface and a lower surface opposite to each other, wherein the film substrate extends in a first direction, and has a first side and a second side that face each other;
• a plurality of wirings provided on the upper surface of the film substrate, wherein the plurality of wirings includes a metal lead portion having an inner lead bonding portion and an outer lead bonding portion, wherein the inner lead bonding portion is at least partially disposed within the chip mounting area, and the outer lead bonding portion extends toward at least one of the first side or the second side from the inner lead bonding portion;
• an upper insulating layer provided on the upper surface of the film substrate and covering the plurality of wirings, wherein the upper insulating layer has a plurality of pad openings and a mounting area opening, wherein the plurality of pad openings expose at least a portion of the outer lead bonding portion, and the mounting area opening exposes at least a portion of the inner lead bonding portion on the chip mounting area;
• a semiconductor chip disposed on the chip mounting area of the film substrate, and bonded to and electrically connected to the exposed inner lead bonding portion;
• and
• a heat dissipation member provided on the upper insulating layer, and having a through opening that exposes the mounting area opening, wherein the heat dissipation member includes a plurality of first extension patterns extending in a second direction that is different from the first direction within the through opening to cover the semiconductor chip.

A semiconductor package, comprising:

• a film substrate having a chip mounting area, and extending in a first direction, wherein the film substrate has a first side and a second side that extend in the first direction and face each other;
• a plurality of wirings provided on the film substrate, wherein the plurality of wirings includes a metal lead portion having an inner lead bonding portion and an outer lead bonding portion, wherein the inner lead bonding portion is at least partially disposed within the chip mounting area, and the outer lead bonding portion extends toward at least one of the first side or the second side from the inner lead bonding portion;
• an upper insulating layer provided on the film substrate and covering the plurality of wirings, wherein the upper insulating layer has a plurality of pad openings and a mounting area opening, wherein the plurality of pad openings expose at least a portion of the outer lead bonding portion, and the mounting area opening exposes at least a portion of the inner lead bonding portion on the chip mounting area;
• a semiconductor chip disposed on the chip mounting area of the film substrate, and bonded to and electrically connected to the exposed inner lead bonding portion;
• and
• a heat dissipation member provided on the upper insulating layer, and having a through opening that exposes the mounting area opening, wherein the heat dissipation member includes a plurality of first extension patterns and at least one second extension pattern, wherein the plurality of first extension patterns extends in a second direction that is different from the first direction within the through opening to cover the semiconductor chip, and the at least one second extension pattern extends in the first direction to intersect the plurality of first extension patterns within the through opening.