Shallow Trench Isolation using Porous Semiconductor

Abstract

Fabrication methods and structures for forming integrated circuit (IC) porous semiconductor (π-Semi) isolation structures such as shallow trench isolation (STI) and/or deep trench isolation (DTI) structures. The methods speed up IC front-end-of-line processing and decrease the cost of IC fabrication. In general, exposed portions of a semiconductor layer are subjected to an electrochemical etching to form π-Semi isolation structures; in essence, the in situ semiconductor is restructured to π-Semi. The characteristics of π-Semi, particularly mesoporous π-Semi and microporous π-Semi, include good electrical insulation as well as hole trapping capability. Accordingly, π-Semi used for STI and/or DTI structures provides excellent electrical isolation. A first embodiment comprises a “pre-FET” π-Semi isolation structure, fabricated before formation of gate, drain, and source structures or regions of a field-effect transistor (FET). A second embodiment comprises a “post-FET” π-Semi isolation structure, fabricated after formation of gate, drain, and source structures or regions of a FET.

Dependencies are inferred from the claim text.