Memory device with a storage component

A memory device comprising:

• a plurality of stacked semiconductor dies comprising:
• a first logic die comprising circuitry configured to:
• transmit commands to a plurality of dies and a second logic die using first TSVs and receive data from the plurality of memory dies and the second logic die using second TSVs;
• the plurality of memory dies comprising circuitry configured to receive commands from the first logic die using the first TSVs and return data to the first logic die using the second TSVs, the plurality of memory dies comprising:
• a first memory die coupled with a first set of the first TSVs but not a second set of the first TSVs;
• and
• a second memory die coupled with the second set of the first TSVs but not the first set of the first TSVs;
• the second logic die comprising circuitry configured to:
• receive commands from the first logic die using the first TSVs, return data to the first logic die using the second TSVs, transmit commands to one or more storage dies using third TSVs, and receive data from the one or more storage dies using fourth TSVs, the second logic die coupled with the first set of the first TSVs and the second set of the first TSVs;
• and
• the one or more storage dies comprising circuitry configured to receive commands from the second logic die using the third TSVs and return data to the second logic die using the fourth TSVs;
• the first TSVs;
• the second TSVs;
• the third TSVs;
• and
• the fourth TSVs.

A memory device comprising:

• a plurality of stacked semiconductor dies comprising:
• a first logic die comprising circuitry configured to:
• transmit commands to one or more dynamic random-access memory (DRAM) dies using at least one first command-address (CA) bus, transmit commands to a second logic die using at least one second CA bus, receive data from the one or more DRAM dies using at least one first data (DQ) bus, and receive data from the second logic die using at least one second DQ bus;
• the one or more DRAM dies comprising circuitry configured to receive commands using the at least one first CA bus and return data using the at least one first DQ bus;
• the second logic die comprising circuitry configured to:
• receive commands using the at least one second CA bus, return data using the at least one second DQ bus, transmit commands to one or more NOT-AND (NAND) dies using at least one third CA bus, and receive data from the one or more NAND dies using at least one third DQ bus;
• and
• the one or more NAND dies comprising circuitry configured to receive commands using the at least one third CA bus and return data using the at least one third DQ bus;
• the at least one first CA bus;
• the at least one second CA bus;
• the at least one third CA bus;
• the at least one first DQ bus;
• the at least one second DQ bus;
• and
• the at least one third DQ bus.