Complementary metal oxide semiconductor circuit of memory device

Abstract

A complementary metal oxide semiconductor (CMOS) circuit includes a high-voltage functional circuit and an auxiliary clamping circuit. The high-voltage functional circuit includes a first metal oxide semiconductor (MOS) transistor. The auxiliary clamping circuit is arranged between an input voltage and a first terminal of the first MOS transistor. The auxiliary clamping circuit includes a first N-type metal oxide semiconductor (NMOS) transistor and a second NMOS transistor coupled in parallel. T first terminal of the first NMOS transistor and a first terminal of the second NMOS transistor are coupled to the input voltage. A second terminal of the first NMOS transistor and a second terminal of the second NMOS transistor are coupled to the first terminal of the first MOS transistor. A gate terminal of the second NMOS transistor is coupled to an output terminal of the high-voltage functional circuit.

Dependencies are inferred from the claim text.