Circuitry for Power Management Assertion
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorSanjeev Kumar Jain
Life of this patent
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Abstract
Circuits and methods are described herein for controlling a bit line precharge circuit. For example, a control circuit includes a first latch circuit and a second latch circuit. The first latch circuit is configured to receive a first light sleep signal. The first latch circuit generates a second light sleep signal according to a clock signal. The second latch circuit is configured to receive the second light sleep signal. The second latch circuit generates a third light sleep signal according to a sense amplifier enable signal. The second latch circuit provides the third light sleep signal to a bit line reading switch, so the bit line reading switch is cutoff after a sense amplifier is enabled.
Claims20
A control circuit comprising:
- a latch circuit configured to provide a first light sleep signal to a bit line reading switch so that the bit line reading switch is cut off after a sense amplifier is enabled, wherein the latch circuit is configured to compare a sense amplifier enable signal and a clock signal.
A read switch driving circuit comprising:
- a latch circuit configured to delay an activation signal to a read switch such that a sense amplifier enable signal precedes the activation signal, wherein the latch circuit is configured to compare the sense amplifier enable signal and a clock signal.
A method of controlling a bit line precharge circuit, comprising:
- providing a sense amplifier enable signal to a latch circuit such that an activation signal to a read switch is asserted after the sense amplifier enable signal, wherein the latch circuit is configured to compare the sense amplifier enable signal and a clock signal.
Dependencies are inferred from the claim text.