Pixel and display device including the same

A display device comprising:

• a display portion including a plurality of pixels, wherein each of the pixels sequentially performs an initialization operation, a threshold voltage compensation operation, a data writing operation, and a light emitting operation during one frame;
• and
• a driving circuit which drives the display portion by providing a data voltage, a first gate signal, a second gate signal, a first power voltage, and a second power voltage to the pixels,
• wherein each of the pixels includes:
• a first transistor including a gate terminal connected to a first node, a first terminal, and a second terminal connected to a second node;
• a second transistor including a gate terminal, to which a first gate signal is applied, a first terminal, to which a data voltage is applied, and a second terminal connected to the first node;
• a third transistor including a gate terminal, to which a second gate signal is applied, a first terminal, to which a first power voltage is applied, and a second terminal connected to the second terminal of the first transistor;
• a first capacitor including a first terminal connected to the first node and a second terminal connected to the second node;
• a second capacitor including a first terminal, to which the first power voltage is applied, and a second terminal connected to the second node;
• and
• a light emitting element including a first terminal connected to the second node and a second terminal, to which a second power voltage is applied.

A display device comprising:

• a display portion which displays an image;
• and
• a driving circuit which drives the display portion by providing a driving signal to the display portion,
• wherein the display portion includes:
• an active layer disposed on a substrate;
• a first gate layer disposed on the active layer and including a first gate electrode;
• a second gate layer disposed on the first gate layer and including a capacitor electrode, wherein the capacitor electrode overlaps the first gate electrode in a plan view and constitutes a first capacitor together with a part of the first gate electrode overlapping the capacitor electrode;
• a first upper conductive layer disposed on the second gate layer and including an additional power line, to which a first power voltage is applied;
• a second upper conductive layer disposed on the first upper conductive layer and including a power line, to which a second power voltage is applied, and a connection pattern connected to the capacitor electrode through a contact hole, wherein the connection pattern partially overlaps the additional power line in the plan view and constitutes a second capacitor together with a part of the additional power line overlapping the connection pattern;
• and
• a pixel electrode disposed on the second upper conductive layer and connected to the connection pattern through a contact hole.