Memory controller with pseudo-channel support

A data processing system, comprising:

• a memory that implements pseudo channels including a first pseudo channel and a second pseudo channel;
• and
• a data processor coupled to the memory, wherein the data processor:
• generates memory access requests;
• routes the memory access requests to a selected one of a first pseudo-channel pipeline circuit and a second pseudo-channel pipeline circuit;
• selects memory access requests in the first pseudo-channel pipeline circuit and the second pseudo-channel pipeline circuit independently;
• and
• provides memory commands to the memory in response to memory access requests selected by the first pseudo-channel pipeline circuit and the second pseudo-channel pipeline circuit.

A method for use in a data processing system having a memory that implements pseudo channels including a first pseudo channel and a second pseudo channel, comprising:

• generating memory access requests;
• routing the memory access requests to a selected one of a first pseudo-channel pipeline circuit and a second pseudo-channel pipeline circuit;
• selecting memory access requests in the first pseudo-channel pipeline circuit and the second pseudo-channel pipeline circuit independently;
• and
• providing memory commands to the memory in response to memory access requests selected by the first pseudo-channel pipeline circuit and the second pseudo-channel pipeline circuit.