US 2025/0061069 A1Published application

Accelerator system and method to execute depthwise separable convolution

AssigneeNational Cheng Kung University

InventorsChung-ho CHEN, Cheng-you XIE

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Abstract

An accelerator system includes an off-chip memory, a bus, and an accelerator. The off-chip memory includes a first buffer. The accelerator includes a second buffer, a third buffer, a fourth buffer, an instruction fetching module, a load module, a storage module, a convolution control module, and a computation module. The instruction fetching module fetches instructions from the off-chip memory via the bus. The load module loads input data from the off-chip memory via the bus. The storage module stores the output data to the off-chip memory via the bus. The computation module performs convolution computations based on the input map and multiple kernels allocated by the convolution module. In response to loading the input data or instruction from the off-chip memory, the requested input data or instruction is transferred from the off-chip memory and temporarily stored in the first buffer.

Claims10

Dependent claims

An accelerator system, comprising:

an off-chip memory comprising a first buffer;
a bus electrically connected to the off-chip memory;
and
an accelerator electrically connected to the bus, comprising:
a second buffer electrically connected to the bus;
a third buffer electrically connected to the bus;
a fourth buffer electrically connected to the bus;
an instruction fetching module electrically connected to the second buffer, and configured to fetch at least one instruction from the off-chip memory via the bus;
a load module electrically connected to the third buffer, and configured to load at least one input data from the off-chip memory via the bus;
a storage module electrically connected to the fourth buffer, and configured to store at least one output data to the off-chip memory via the bus;
a convolution control module electrically connected to the instruction fetching module, the load module, and the storage module;
and
a computation module electrically connected to the convolution control module, the load module, and the storage module, and configured to perform convolution computations based on an input map and a plurality of kernels allocated by the convolution control module;
wherein in response to a request from the accelerator for loading the at least one input data or the at least one instruction from the off-chip memory, the requested at least one input data or the requested at least one instruction is transferred from the off-chip memory and temporarily stored in the first buffer.

11 more elements

Dependencies are inferred from the claim text.