Configuring pci express module using hardware in a memory sub-system
AssigneeMicron Technology, Inc.
InventorMelky Arputharaja Siluvainathan
Life of this patent
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Abstract
A first set of parameter values are programed to a first set of sequencer registers. A second set of parameter values are programmed to a second set of sequencer registers. In response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.
Claims20
A memory sub-system comprising:
- a memory device;
- a hardware sequencer comprising a plurality of sequencer registers;
- a processing device, operatively coupled with the memory device, to perform operations comprising:
- programming a first set of parameter values to a first set of sequencer registers of the plurality of sequencer registers, and a second set of parameter values to a second set of sequencer registers of the plurality of sequencer registers;
- and
- responsive to detecting a triggering event, the hardware sequencer to perform operations comprising:
- transferring the first set of parameter values from the first set of sequencer registers to a first set of link training registers of a plurality of link training registers of the memory sub-system;
- transferring the second set of parameter values from the second set of sequencer registers to a second set of link training registers of the plurality of link training registers of the memory sub-system;
- and
- initiating one end of a communication link training with a host.
A method comprising:
- programming, by a processing device, a first set of parameter values to a first set of sequencer registers of a plurality of sequencer registers of a memory sub-system, and a second set of parameter values to a second set of sequencer registers of the plurality of sequencer registers;
- and
- responsive to detecting a triggering event, performing, by a hardware sequencer operations comprising:
- transferring the first set of parameter values from the first set of sequencer registers to a first set of link training registers of a plurality of link training registers of the memory sub-system;
- transferring the second set of parameter values from the second set of sequencer registers to a second set of link training registers of the plurality of link training registers of the memory sub-system;
- and
- initiating one end of a communication link training with a host.
A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a controller managing a memory device comprising a plurality of memory cells, cause the controller to:
- program a first set of parameter values to a first set of sequencer registers of a plurality of sequencer registers of a memory sub-system, and a second set of parameter values to a second set of sequencer registers of the plurality of sequencer registers;
- and
- responsive to detecting a triggering event, perform, by a hardware sequencer, operations comprising:
- transferring the first set of parameter values from the first set of sequencer registers to a first set of link training registers of a plurality of link training registers of the memory sub-system;
- transferring the second set of parameter values from the second set of sequencer registers to a second set of link training registers of the plurality of link training registers of the memory sub-system;
- enabling a configuration mode of the memory sub-system, wherein the configuration mode permits a host to obtain values from the plurality of link training registers;
- and
- initiating one end of a communication link training with the host.
Dependencies are inferred from the claim text.