Memory address protection circuit and method of operating same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSaman M. I. ADHAM, Ramin SHARIAT-YAZDI, Shih-Lien Linus LU
Life of this patent
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Abstract
A memory circuit includes: a memory configured to store a data unit and a corresponding first code; a decoding circuit configured to do as follows including, generate a second code based on a read address associated with the stored data unit, and generate a decoded write address based on the second code; a first error detecting circuit configured to do as follows including, determine an address fault by performing a first comparison between the read address and the decoded write address, and generate an error signal indicative of a result of the first comparison.
Claims20
A memory circuit comprising:
- a memory configured to store a data unit and a corresponding first code;
- a decoding circuit configured to do as follows including,
- generate a second code based on a read address associated with the stored data unit, and
- generate a decoded write address based on the second code;
- a first error detecting circuit configured to do as follows including,
- determine an address fault by performing a first comparison between the read address and the decoded write address, and
- generate an error signal indicative of a result of the first comparison.
A memory circuit comprising:
- an encoding circuit configured to generate a first code based on a data unit and a second code based on a write address associated with a stored data unit;
- a memory configured to store the data unit and the first and second codes;
- a decoding circuit configured to do as follows including,
- output the stored data unit based on a read address associated with the stored data unit,
- generate a data unit error signal based on the stored data unit and the first code, the data unit error signal being indicative of an error in the stored data unit, and
- generate a decoded write address based on the read address and a third code;
- and
- an error detecting circuit configured to do as follows including,
- determine an address fault by performing a comparison between the read address and the decoded write address, and
- generate an address error signal indicative of a result of comparison.
A method of operating a memory circuit, the method comprising:
- receiving a read address associated with a data unit stored in the memory circuit;
- receiving a first code associated with the stored data unit;
- generating a second code based on the read address;
- generating a decoded write address based on the second code;
- determining an address fault by performing a comparison between the read address and the decoded write address and the read address;
- and
- generating an error signal indicative of a result of comparison.
Dependencies are inferred from the claim text.