In-memory computing devices for multiply accumulate

A memory circuit, comprising:

• a set of memory cells configured to store a weight number having a first number of bits;
• a control circuit configured to provide an input number to an in-memory computing (IMC) circuit, wherein the input number has a second number of bits;
• and
• the in-memory computing (IMC) circuit comprising a matrix of IMC cells having a total number of IMC cells configured to receive in parallel the second number of bits of the input number and perform bit-wise multiplications in parallel, wherein an IMC cell of the matrix of IMC cells comprises a bit-wise multiplication circuit configured to multiply a first bit of the input number and a second bit of the weight number, and wherein the total number is a product of the first number and the second number.

A method, comprising:

• generating, by a bit-wise multiplication circuit, a bit-wise product by multiplying a bit of a weight number having a first number of bits and a bit of an input number having a second number of bits;
• generating, by a first set of in-memory computing (IMC) cells, a first bit-product of the weight number and a first bit of the input number, wherein the first bit-product comprises the first number of bits, and wherein a bit of the first bit-product comprises a first bit-wise product generated by a first bit-wise multiplication circuit;
• and
• generating, by a second set of IMC cells comprising a first number of IMC cells, a second bit-product of the weight number and a second bit of the input number, wherein the second bit-product comprises the first number of bits, and wherein a bit of the second bit-product comprises a second bit-wise product generated by a second bit-wise multiplication circuit.