Memory device, memory module including the memory device, and operating method of memory controller
AssigneeSamsung Electronics Co., Ltd.
InventorsDEOKHO SEO, TAEKYEONG KO, NAMHYUNG KIM, DAEJEONG KIM, DOHAN KIM, HOYOUNG LEE, INSU CHOI
Life of this patent
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Abstract
A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.
Claims18
An operating method of a memory controller, the method comprising:
- transmitting a normal read command to a memory device;
- receiving, in response to the normal read command, miscorrected data generated by miscorrecting first data through an on-die error correction code (ECC) operation of the memory device;
- transmitting, to the memory device, a first uncorrected read command for receiving second data in a state in which an error bit in the first data is not corrected;
- and
- receiving the second data from the memory device.
A memory device, comprising:
- a printed circuit substrate;
- and
- a plurality of memory chips mounted on the printed circuit substrate,
- wherein each of the plurality of memory chips comprises:
- a memory cell array that stores first data;
- and
- an error correction code (ECC) engine configured to correct an error bit in the first data and output the corrected data, in response to receiving a normal read command from a memory controller, and to output second data in a state in which the error bit in the first data is not corrected, in response to receiving an uncorrected read command from the memory controller,
- wherein the ECC engine is further configured to transmit, in response to the normal read command, miscorrected data generated by miscorrecting the error bit in the first data to the memory controller, and to receive the uncorrected read command in response to the transmission of the miscorrected data.
An operating method of a memory device, the method comprising:
- receiving a normal read command from a memory controller;
- in response to the normal read command, transmitting, to the memory controller, miscorrected data generated by miscorrecting first data through an on-die error correction code (ECC) operation;
- receiving, from the memory controller, a first uncorrected read command for transmitting second data in a state in which an error bit in the first data is not corrected;
- and
- transmitting the second data to the memory controller.
Dependencies are inferred from the claim text.