US 2025/0060874 A1 · SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes terminals connectable to a host, first and second bridge chips connected to the terminals, first chips connected to the first bridge chip, and second chips connected to the second bridge chip. The terminals includes a first terminal through which a first signal designating a bridge chip is transmitted. The first bridge chip is configured to enable signal transmission to at least one of the first chips when the first signal designates the first bridge chip, and disable the signal transmission to the first chips when the first signal does not designate the first bridge chip. The second bridge chip is configured to enable signal transmission to at least one of the second chips when the first signal designates the second bridge chip, and disable the signal transmission to the second chips when the first signal does not designate the second bridge chip.

Claims7

Dependent claims

A host device comprising:

a plurality of terminals commonly connectable to a plurality of bridge chips via a plurality of signal lines, the plurality of signal lines including data signal lines, each of the bridge chips being connectable to a plurality of chips;
and
a controller configured to issue a first command and transmit the first command via the data signal lines to the plurality of bridge chips, the first command including first address information that designates one of the plurality of bridge chips and second address information that designates one of the plurality of chips connected to the designated one of the bridge chips, wherein
the controller is configured to swap an order in which the information contained in the first command is issued.

1 more element

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims7