Configurable cache for coherent system
AssigneeTexas Instruments Incorporated
InventorsKai CHIRCA, Matthew David PIERSON
Life of this patent
Estimating the term…
Abstract
A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.
Claims20
A device comprising:
- a controller configurable to receive an access request including a memory address from a peripheral;
- and
- a cache configuration register coupled to the controller and configured to store a first mask bit associated with the peripheral,
- wherein the controller is configurable to:
- perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit;
- and
- allocate a cache way to a cache tag associated with the memory address using the first output bit.
A method comprising:
- receiving an access request including a memory address from a peripheral;
- retrieving a first mask bit associated with the peripheral from a cache configuration register;
- performing a first logical operation with a first pointer bit and the first mask bit to generate a first output bit;
- and
- allocating a cache way to a cache tag associated with the memory address using the first output bit.
A system comprising:
- a memory cache including a cache way;
- a peripheral;
- a cache controller configurable to receive an access request including a memory address from the peripheral;
- and
- a cache configuration register coupled to the cache controller and configured to store a first mask bit associated with the peripheral,
- wherein the cache controller is configurable to:
- perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit;
- and
- allocate the cache way to a cache tag associated with the memory address using the first output bit.
Dependencies are inferred from the claim text.