Information processing device
AssigneeToyota Jidosha Kabushiki Kaisha
InventorsSatofumi KURISU, Kosuke OHASHI, Ryo ANAN, Ryota NAKABAYASHI, Nobutaka SUZUKI, Kiyoto SUZUKI
Life of this patent
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Abstract
The information processing device includes a CPU, DRAM, SRAM and hibernation circuitry. The hibernation circuit executes an evacuation processing of reading out particular data which is data stored in DRAM and storing the particular data in SRAM when a predetermined execution condition for hibernation is satisfied. CPU shuts off the electric power supply to DRAM while maintaining the electric power supply to SRAM after the evacuation processing is completed. When startup, CPU reads out the particular data stored in SRAM when the particular data is stored in SRAM.
Claims5
An information processing device, comprising:
- a main processing circuit that is configured to realize various types of processing by executing a program;
- dynamic random-access memory (DRAM) that is volatile memory and that requires refresh processing to retain data;
- static random-access memory (SRAM) that is volatile memory and does not require refresh processing to retain data;
- and
- a sub-processing circuit that is configured to realize evacuation processing of reading particular data that is data stored in the DRAM and performing storage thereof in the SRAM, wherein
- when an execution condition for hibernation that is set in advance is satisfied, the sub-processing circuit executes the evacuation processing,
- after the evacuation processing is completed, the main processing circuit cuts off electric power supply to the DRAM while maintaining electric power supply to the SRAM, and
- at startup, when the particular data is stored in the SRAM, the main processing circuit reads the particular data stored in the SRAM.
Dependencies are inferred from the claim text.