System, method and apparatus for reactive power control in a processor

A system comprising:

• a voltage regulator to receive a system voltage and output an operating voltage;
• a voltage regulator controller to identify when the system voltage falls below a threshold voltage;
• a system on chip (SoC) coupled to the voltage regulator, the SoC to receive the operating voltage and comprising:
• at least one first intellectual property (IP) circuit to execute operations on first data;
• at least one second IP circuit to execute operations on second data;
• and
• a power controller to:
• receive a boost value, the boost value based at least in part on one or more characteristics of the voltage regulator;
• determine a boosted maximum power level for the SoC based at least in part on the boost value and a legacy maximum power level for the SoC, the boosted maximum power level greater than the legacy maximum power level;
• and
• determine a boosted maximum power budget for the at least one first IP circuit based at least in part on the boosted maximum power level, the boosted maximum power budget for the at least one first IP circuit greater than a legacy maximum power budget for the at least one first IP circuit,
• wherein the at least one first IP circuit, is to reduce power consumption equal to or below the legacy maximum power budget for the at least one the first IP circuit, in reaction to the input voltage falling below the threshold voltage;
• and
• a non-volatile memory coupled to the SoC.