Timed triggers on a 1-wire rffe bus
AssigneeQUALCOMM Incorporated
InventorsLalan Jee MISHRA, Umesh SRIKANTIAH, Richard Dominic WIETFELDT
Life of this patent
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AssigneeQUALCOMM Incorporated
InventorsLalan Jee MISHRA, Umesh SRIKANTIAH, Richard Dominic WIETFELDT
Estimating the term…
A receiving device, comprising: a clock generator circuit configured to generate a base clock signal; a counter configured to count cycles or edges of the base clock signal while a measurement pulse is received over a one-wire serial bus during a first transaction conducted over the one-wire serial bus, the measurement pulse having a pulse duration defined by a number of clock cycles of a transmitter clock signal; and a controller configured to adjust a count value of the counter when the counter is timing actuation of a trigger using a correction value that represents a difference between the cycles or edges of the base clock signal counted while the measurement pulse was being received and the number of clock cycles of the transmitter clock signal that defines the pulse duration.
A receiving device, comprising:
A method for timing triggers in a receiving device, comprising:
A system, comprising:
Dependencies are inferred from the claim text.