Low dropout regulators

A low dropout (LDO) regulator comprising:

• a first low voltage transistor comprising:
• a first terminal connected to an output node, the output node being configured to provide an output voltage to a load, and
• a second terminal connected to a first node;
• an operational amplifier configured to (i) compare a reference voltage with the output voltage to obtain a comparison result, and (ii) output the comparison result to a gate terminal of the first low voltage transistor;
• a first high voltage transistor comprising a first terminal connected to a high power voltage terminal and a second terminal connected to the output node;
• and
• a second high voltage transistor comprising a first terminal connected to a gate terminal of the first high voltage transistor and a second terminal connected to the first node,
• wherein the second high voltage transistor has a different channel type than the first high voltage transistor and the first low voltage transistor.

A memory device comprising:

• a buffer die;
• and
• a plurality of core dies vertically stacked on the buffer die and connected to the buffer die via a plurality of through silicon vias (TSV),
• wherein the buffer die comprises:
• a first driving circuit configured to generate first output data from first input data and output the generated first output data to a first TSV of the plurality of TSVs;
• and
• a first low dropout (LDO) regulator configured to provide a first output voltage of a first output node to the first driving circuit as a first supply voltage,
• wherein the first LDO regulator comprises:
• a first low voltage transistor comprising a first terminal connected to the first output node and a second terminal connected to a first node;
• a first operational amplifier configured to (i) compare a first reference voltage with the first output voltage to obtain a first comparison result, and (ii) output the first comparison result to a gate terminal of the first low voltage transistor;
• and
• a first operation biasing control circuit connected to the first output node and the first node and including at least one first high voltage transistor,
• wherein the first operation biasing control circuit is configured to control a bias on the first low voltage transistor based on a pre-defined first voltage.