Low dropout regulator and memory device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJunhan Choi, Jaewoo Park, Myoungbo Kwak, Jinook Jung
Life of this patent
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Abstract
An example low dropout (LDO) regulator includes a voltage regulating circuit and an adaptive biasing circuit. The voltage regulating circuit is configured to regulate an output voltage of an output node connected with a load by using the output voltage as first feedback. The adaptive biasing circuit is configured to generate a biasing signal that supports regulation of the output voltage by using a sensing signal in an internal node of the voltage regulating circuit as second feedback, and to provide the biasing signal to the voltage regulating circuit.
Claims24
A low dropout (LDO) regulator comprising:
- a voltage regulating circuit configured to regulate an output voltage of an output node, the output node being connected with a load, the output voltage being used as first feedback;
- and
- an adaptive biasing circuit configured to
- generate a biasing signal configured to regulate the output voltage based on a sensing signal in an internal node of the voltage regulating circuit, the sensing signal being used as second feedback, and
- provide the biasing signal to the voltage regulating circuit.
(canceled)
(canceled)
A low dropout (LDO) regulator comprising:
- a first node connected with a load and configured to provide an output voltage;
- an LDO current source connected between a second node and ground and configured to drive a sink current;
- a first current mirror comprising a first transistor and a second transistor that are connected with a power voltage terminal through a source terminal of each of the first transistor and the second transistor and with the second node through a gate terminal of each of the first transistor and the second transistor;
- a third transistor sharing the first node with a drain terminal of the first transistor through a source terminal of the third transistor, the third transistor being connected with the second node through a drain terminal of the third transistor;
- a comparator configured to output, to a gate terminal of the third transistor, a result of comparing an output voltage of the first node with a reference voltage;
- and
- an adaptive biasing circuit configured to generate an additional current to complement the sink current based on a sensing signal corresponding to a voltage of the second node, the additional current flowing from the second node to ground.
(canceled)
A memory device comprising:
- a buffer die;
- and
- a plurality of core dies vertically stacked on the buffer die, the plurality of core dies being connected with the buffer die through a plurality of through silicon vias (TSVs),
- wherein the buffer die comprises
- a first driving circuit configured to
- generate first output data from first input data, and
- output the first output data to a first TSV among the plurality of TSVs;
- and
- a first low dropout (LDO) regulator configured to provide, as a first supply voltage, a first output voltage of a first output node to the first driving circuit,
- wherein the first LDO regulator comprises
- a first voltage regulating circuit configured to regulate the first output voltage of the first output node based on the first output voltage;
- and
- a first adaptive biasing circuit configured to generate a first biasing signal configured to regulate the first output voltage based on a first sensing signal in a first internal node of the first voltage regulating circuit.
-26. (canceled)
Dependencies are inferred from the claim text.