Touch panel

A touch panel comprising:

• a first transistor, a second transistor, a capacitor, and a touch sensor over a first substrate;
• a first insulating layer over the first transistor, the second transistor, and the capacitor;
• a second insulating layer over the first insulating layer;
• a light-emitting element over the second insulating layer;
• a second substrate over the light-emitting element;
• and
• a polarizing plate overlapping with the light-emitting element,
• wherein the first transistor comprises a first gate electrode, a first semiconductor layer, and a first gate insulating layer between the first gate electrode and the first semiconductor layer,
• wherein the second transistor comprises a second semiconductor layer,
• wherein the touch panel further comprises:
• a first conductive layer over the second substrate;
• and
• a second conductive layer over the first gate insulating layer,
• wherein the first conductive layer comprises a first portion configured to function as the first gate electrode of the first transistor and a second portion configured to function as one electrode of the capacitor, and
• wherein the second conductive layer comprises a first portion in contact with the first conductive layer and a second portion configured to function as one of a source electrode and a drain electrode of the second transistor.

A touch panel comprising:

• a first transistor, a second transistor, a capacitor, and a touch sensor over a first substrate;
• and
• a polarizing plate below the first substrate,
• wherein the first transistor comprises a first gate electrode, a first semiconductor layer, and a first gate insulating layer between the first gate electrode and the first semiconductor layer,
• wherein the second transistor comprises a second semiconductor layer,
• wherein the touch panel further comprises:
• a first conductive layer over the second substrate;
• and
• a second conductive layer over the first gate insulating layer,
• wherein the first conductive layer comprises a first portion configured to function as the first gate electrode of the first transistor and a second portion configured to function as one electrode of the capacitor, and
• wherein the second conductive layer comprises a first portion in contact with the first conductive layer and a second portion configured to function as one of a source electrode and a drain electrode of the second transistor.