Fractional frequency divider and flash memory controller

A flash memory controller, wherein the flash memory controller is coupled to a flash memory module, the flash memory module comprises at least one flash memory chip, and the flash memory controller comprising:

• a memory, for storing a program code;
• a microprocessor, configured to execute the program code to access the flash memory module;
• and
• a control logic, configured to control the flash memory module, wherein the control logic comprises:
• a clock signal generator, configured to generate a clock signal and an input clock signal;
• a fractional frequency divider, configured to receive the input clock signal to generate an output clock signal;
• and
• a digital circuit;
• wherein when the flash memory controller operates in a normal mode, the fractional frequency divider does not mask any part of the input clock signal to generate the output clock signal, and the digital circuit works by using the output clock signal which is equal to the input clock signal;
• and when the flash memory controller operates in a power saving mode, the fractional frequency divider masks part of the input clock signal to generate the output clock signal, and the digital circuit works by using the output clock signal.