Programmable logic device and methods of implementing logic circuits to it
AssigneeNational University Corporation Kumamoto University
InventorMasahiro IIDA
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Abstract
In the conventional eFPGAs, there have been two challenges: the first one being size reduction of the logic cells to improve the implemented logic density, and the second one being minimization of the speed difference with the ASIC. According to the present embodiment, there is provided a method for configuring a programmable logic circuit represented by a gate-level netlist, wherein this is done by assigning the gate-level netlist to a 4-input, 3-output combinational logic cell, which is composed of a combination of 3 of 2-input (m-input) basic logic cells, wherein the combinational logic cell covers 3(n) nodes constituting a graph of the netlist.
Claims11
A programmable logic circuit, comprising:
- a basic logic cell for configuring a plurality of nodes of a gate-level netlist,
- wherein the basic logic cell is a programmable circuit configured by adding one or more programmable NOT circuits to a basic logic operation element and made programmable to switch inputs and outputs of the basic logic cell depending on connection relationships of nodes in the gate-level netlist.
A method for configuring a programmable logic circuit, wherein
- nodes constituting a gate-level netlist are assigned to a programmable logic cell, and
- the programmable logic cell is made programmable to switch inputs and outputs of the logic cell depending on connection relationships of the nodes.
Dependencies are inferred from the claim text.