Vcsel chip structure for quick test and method for forming the same

Abstract

A VCSEL chip structure for quick test and a method for forming the same are provided. The VCSEL chip structure has probing and emission regions divided by a first trench, and includes a substrate, an epitaxial layer, a cap layer, and first and second electrodes. The epitaxial layer is formed on a top surface of the substrate. The cap layer is formed on the epitaxial layer. The first electrode is formed on the cap layer and on a bottom and two sidewalls of the first trench. The second electrode is formed on a bottom surface of the substrate. The probing region has multiple second trenches which divide the probing region into multiple sub-regions. The epitaxial layer in the emission region has a first wet oxidation layer with an aperture. The epitaxial layer in each sub-region of the probing region has a second wet oxidation layer spanning the respective sub-region.

Dependencies are inferred from the claim text.