US 2025/0054528 A1 · SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESET, AND DATA CORRUPTION MODES FOR SECURE APPLICATIONS

Abstract

A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

Claims18

Dependent claims

A method of corrupting contents of a memory array, comprising:

a) asserting a signal at a reset node to thereby cause starving of current supply to the memory array;
b) selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted;
c) for each desired column, forcing a logic state of its bit line and complementary bit line to a same logic state;
and
d) simultaneously asserting each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted, and then simultaneously deasserting those word lines to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

2 more elements

A static random access memory (SRAM) device, comprising:

a virtual power supply circuit configured to generate a virtual power supply voltage;
a memory array powered between the virtual power supply voltage and a reference voltage, the memory array being comprised of memory cells and being organized into rows and columns, with each row having a word line associated therewith and each column having a bit line and complementary bit line associated therewith;
a row decoder configured to selectively assert word lines of desired rows;
a column decoder configured to select desired columns;
wherein the virtual power supply circuit is configured to reduce its current output so as to starve the memory array, in response to an internal clock signal pulse;
and
column driving circuitry configured to, in response to being clocked by the internal clock signal pulse and assertion of a latched reset signal, drive the bit lines and the complementary bit lines of the desired columns to a same logic state;
wherein, in response to being clocked by the internal clock signal pulse and based upon the latched reset signal, the row decoder simultaneously asserts the word lines of each desired row;
and
wherein, in response to an end of the internal clock signal pulse, the row decoder simultaneously deasserts the word lines of each desired row, thereby placing the memory cells belonging to the desired rows and the desired columns into a metastable state.

7 more elements

Dependencies are inferred from the claim text.

Sram with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications

Life of this patent

Sram with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications

Life of this patent

Abstract

Claims18