Semiconductor device

A system comprising:

• a connector;
• a volatile semiconductor memory;
• first to n-th nonvolatile semiconductor memories (n is an integer equal to or larger than two), each including a plurality of ball-shaped electrodes on a bottom surface;
• a controller configured to control the volatile semiconductor memory and the first to n-th nonvolatile semiconductor memories;
• first to n-th circuit elements, each including a first electrode, a second electrode, a film provided between the first electrode and the second electrode, and a coat covering the film;
• a multilayer wiring substrate on which the volatile semiconductor memory, the first to n-th nonvolatile semiconductor memories, the first to n-th circuit elements, the controller, and the connector are mounted, the multilayer wiring substrate being shaped as a rectangle in a plan view, the connector being provided on a short side of the rectangle;
• and
• a processing circuitry being connected to the connector, wherein
• the first to n-th nonvolatile semiconductor memories are aligned on a line in a longitudinal direction of the multilayer wiring substrate,
• the controller is provided, in a plan view, between the connector and the first to n-th nonvolatile semiconductor memories,
• the multilayer wiring substrate includes
• a front surface layer with a wiring pattern formed thereon, the front surface layer being a layer on which the volatile semiconductor memory, the first to n-th nonvolatile semiconductor memories, and the controller are mounted;
• a rear surface layer with a wiring pattern formed thereon, the rear surface layer being a layer on which (n+1)-th to 2n-th nonvolatile semiconductor memories each including a plurality of ball-shaped electrodes on a bottom surface are mounted such that the (n+1)-th to 2n-th nonvolatile semiconductor memories are symmetric to the first to n-th nonvolatile semiconductor memories with respect to the multilayer wiring substrate,
• a plurality of internal wiring layers that is provided between the front surface layer and the rear surface layer, the plurality of internal wiring layers having a wiring pattern formed thereon,
• first to n-th signal lines that connect the controller to the first to n-th circuit elements, respectively;
• (n+1)-th to 2n-th signal lines that connect the first to n-th circuit elements to the first to n-th nonvolatile semiconductor memories, respectively, the (n+1)-th to 2n-th signal lines having a part that passes through the internal wiring layers;
• and
• (2n+1)-th to 3n-th signal lines that branch from the (n+1)-th to 2n-th signal lines and connect the (n+1)-th to 2n-th nonvolatile semiconductor memories, respectively.