CASCADE PROTOCOL FOR iSWAP GATE IN A TWO-QUBIT SYSTEM

An apparatus comprising:

• a classical processor configured to perform operations for generating a cascade schedule for implementations of an iSWAP quantum logic gate, the operations comprising:
• synchronizing errors in a swap channel and a leakage channel to generate a cascade schedule for driving a detuning between a frequency of a first qubit and a frequency of a second qubit, comprising:
• selecting a solution in the swap channel that, when combined with a probability of an error in the leakage channel, achieves a predetermined swap gate fidelity;
• and
• applying values of parameters in the selected solution to an initial schedule for driving the detuning between a frequency of the first qubit and a frequency of the second qubit;
• the first qubit;
• the second qubit, wherein the second qubit is coupled to the first qubit;
• control electronics comprising one or more control devices that tune the frequency of the first qubit and the frequency of the second qubit through application of respective control signals, wherein the control electronics are configured to implement the cascade schedule by:
• adiabatically driving the detuning between the frequency of the first qubit and the frequency of the second qubit through a first avoided crossing in the leakage channel;
• and
• driving the detuning between the frequency of the first qubit and the frequency of the second qubit through a second avoided crossing in the swap channel.