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US 2025/0053810 A1Published application
Queue Allocation in Machine Learning Accelerators
AssigneeGoogle Inc.
InventorsXiangyu Dong, Kais Belgaied, Yazhou Zu
Life of this patent
Estimating the term…
Abstract
This disclosure generally provides solutions for improving the performance of a custom-built, packet-switched, TPU accelerator-side communication network. Specifically a set of solutions to improve the flow-control behavior by tuning the packet buffer queues in the on-chip router in the distributed training supercomputer network are described.
Claims20
A method comprising:
- accessing data associated with a plurality of communications ports of an application specific integrated circuit (ASIC) comprising multiple processing units, wherein the data identifies, for each communications port of the plurality of communications ports, whether the communications port is used in a current topology of the multiple processing units and a communications medium associated with the communications port;
- determining an expected latency for each communications port of the plurality of communications ports based on the accessed data;
- and
- allocating portions of a shared memory to each communications port of the plurality of communications ports, the allocating comprising:
- determining a memory allocation for each communications port based on the expected latency;
- and
- assigning a start address and a stop address of the shared memory to each communications port based on the memory allocation for each communications port.
4 more elements
A system, comprising:
- one or more memory devices storing instructions;
- and
- one or more data processing apparatus that are configured to interact with the one or more memory devices, and upon execution of the instructions, perform operations including:
- accessing data associated with a plurality of communications ports of an application specific integrated circuit (ASIC) comprising multiple processing units, wherein the data identifies, for each communications port of the plurality of communications ports, whether the communications port is used in a current topology of the multiple processing units and a communications medium associated with the communications port;
- determining an expected latency for each communications port of the plurality of communications ports based on the accessed data;
- and
- allocating portions of a shared memory to each communications port of the plurality of communications ports, the allocating comprising:
- determining a memory allocation for each communications port based on the expected latency;
- and
- assigning a start address and a stop address of the shared memory to each communications port based on the memory allocation for each communications port.
7 more elements
A non-transitory computer readable medium storing instructions that, when executed by one or more data processing apparatus, cause the one or more data processing apparatus to perform operations comprising:
- accessing data associated with a plurality of communications ports of an application specific integrated circuit (ASIC) comprising multiple processing units, wherein the data identifies, for each communications port of the plurality of communications ports, whether the communications port is used in a current topology of the multiple processing units and a communications medium associated with the communications port;
- determining an expected latency for each communications port of the plurality of communications ports based on the accessed data;
- and
- allocating portions of a shared memory to each communications port of the plurality of communications ports, the allocating comprising:
- determining a memory allocation for each communications port based on the expected latency;
- and
- assigning a start address and a stop address of the shared memory to each communications port based on the memory allocation for each communications port.
4 more elements
Dependencies are inferred from the claim text.