Compute optimization mechanism for deep neural networks

An apparatus, comprising:

• at least one processor;
• and
• a graphics processing unit (GPU) including circuitry configured to execute instructions, the circuitry comprising:
• processing circuitry configured to perform general-purpose graphics computations, the processing circuitry including a single instruction multiple thread (SIMT) architecture;
• a graph processing unit (GrPU) including instruction execution circuitry configured to accelerate computations on a graph representation in response to a request from the processing circuitry, wherein the GrPU includes multiple single instruction multiple data (SIMD) hardware threads to concurrently traverse multiple graph representations and execute instructions associated with the multiple graph representations;
• and
• a compilation unit (CU) including instruction execution circuitry configured to dynamically compile shader kernels locally on the GPU.

A data processing system comprising:

• a memory device to store instructions;
• and
• a heterogeneous processor comprising a central processing unit (CPU), a graphics processing unit (GPU), and a compute accelerator, the heterogeneous processor including circuitry comprising:
• processing circuitry configured to perform general-purpose graphics computations, the processing circuitry including a single instruction multiple thread (SIMT) architecture;
• a graph processing unit (GrPU) including instruction execution circuitry configured to accelerate computations on a graph representation in response to a request from the processing circuitry, wherein the GrPU includes multiple single instruction multiple data (SIMD) hardware threads to concurrently traverse multiple graph representations and execute instructions associated with the multiple graph representations;
• and
• a compilation unit (CU) including instruction execution circuitry configured to dynamically compile shader kernels locally on the GPU.