Generating integrated circuit floorplans using neural networks

A method performed by one or more computers, the method comprising:

• obtaining netlist data for a computer chip, wherein the netlist data specifies a connectivity on a computer chip between a plurality of nodes that each correspond to one or more of a plurality of integrated circuit components of the computer chip, wherein the plurality of nodes comprises nodes representing at least macros and nodes representing clusters of standard cells;
• and
• generating a computer chip floorplan that places each node in the netlist data at a respective position on the surface of the computer chip, comprising:
• placing at least the nodes representing the macros on the surface of the computer chip, comprising placing a respective node at each of a plurality of time steps in a sequence of time steps, the placing comprising, for a particular time step of the plurality of time steps:
• processing an input representation for the particular time step using a node placement neural network to generate a score distribution having a respective score for each of a plurality of positions on the surface of the computer chip;
• generating a modified score distribution that sets to zero the respective score for one or more of the plurality of positions based on respective densities for the plurality of positions that are determined based on respective positions on the surface of the chip of nodes that have already been placed at time steps preceding the particular time step in the sequence;
• and
• assigning the node using the modified score distribution.

A system comprising one or more computers and one or more storage devices storing instructions that when executed by the one or more computers cause the one or more computers to perform operations comprising:

• obtaining netlist data for a computer chip, wherein the netlist data specifies a connectivity on a computer chip between a plurality of nodes that each correspond to one or more of a plurality of integrated circuit components of the computer chip, wherein the plurality of nodes comprises nodes representing at least macros and nodes representing clusters of standard cells;
• and
• generating a computer chip floorplan that places each node in the netlist data at a respective position on the surface of the computer chip, comprising:
• placing at least the nodes representing the macros on the surface of the computer chip, comprising placing a respective node at each of a plurality of time steps in a sequence of time steps, the placing comprising, for a particular time step of the plurality of time steps:
• processing an input representation for the particular time step using a node placement neural network to generate a score distribution having a respective score for each of a plurality of positions on the surface of the computer chip;
• generating a modified score distribution that sets to zero the respective score for one or more of the plurality of positions based on respective densities for the plurality of positions that are determined based on respective positions on the surface of the chip of nodes that have already been placed at time steps preceding the particular time step in the sequence;
• and
• assigning the node using the modified score distribution.

One or more non-transitory computer-readable storage media storing instructions that when executed by one or more computers cause the one or more computers to perform operations comprising:

• obtaining netlist data for a computer chip, wherein the netlist data specifies a connectivity on a computer chip between a plurality of nodes that each correspond to one or more of a plurality of integrated circuit components of the computer chip, wherein the plurality of nodes comprises nodes representing at least macros and nodes representing clusters of standard cells;
• and
• generating a computer chip floorplan that places each node in the netlist data at a respective position on the surface of the computer chip, comprising:
• placing at least the nodes representing the macros on the surface of the computer chip, comprising placing a respective node at each of a plurality of time steps in a sequence of time steps, the placing comprising, for a particular time step of the plurality of time steps:
• processing an input representation for the particular time step using a node placement neural network to generate a score distribution having a respective score for each of a plurality of positions on the surface of the computer chip;
• generating a modified score distribution that sets to zero the respective score for one or more of the plurality of positions based on respective densities for the plurality of positions that are determined based on respective positions on the surface of the chip of nodes that have already been placed at time steps preceding the particular time step in the sequence;
• and
• assigning the node using the modified score distribution.