Secure Public Key Acceleration

A system on a chip (SoC), comprising:

• one or more processors;
• and
• a security circuit that includes an internal processor, a read-only memory (ROM), and a cryptographic accelerator circuit isolated from the one or more processors, wherein the security circuit is configured to:
• boot the security circuit using boot code stored in the ROM and executed by the internal processor;
• and
• perform, via the cryptographic accelerator circuit, a public-key cryptographic operation responsive to a service request associated with the one or more processors, wherein performance of the public-key cryptographic operation includes accessing key material stored in an internal memory of the cryptographic accelerator circuit.

A device, comprising:

• an integrated circuit that includes one or more processors and a security circuit having an internal processor, a read-only memory (ROM), and cryptographic accelerator circuit isolated from the one or more processors, wherein the security circuit is configured to:
• boot the security circuit via the internal processor executing boot code stored in the ROM;
• receive a service request associated with the one or more processors;
• and
• perform, via the cryptographic accelerator circuit, a public-key cryptographic operation responsive to the service request, wherein performance of the public-key cryptographic operation includes accessing key material stored in an internal memory of the cryptographic accelerator circuit.

One or more non-transitory computer readable media having program instructions stored therein that are executable by a device to perform operations comprising:

• booting a security circuit of the device, wherein the booting includes an internal processor of the security circuit executing boot code stored in a read-only memory (ROM) included in the security circuit;
• receiving, by the security circuit and from a processor external to the security circuit, a request for performance of a cryptographic operation;
• and
• performing, by a cryptographic accelerator circuit included in the security circuit and isolated from the external processor, the cryptographic operation, wherein performance of the cryptographic operation includes accessing key material stored in an internal memory of the cryptographic accelerator circuit.