Microarchitectural mechanisms for the prevention of side-channel attacks using a thread identification (tid) and a privilege level bit

A method comprising:

• fetching instructions by an instruction fetch circuit of a hardware processor core;
• storing a plurality of entries that each include an address space identifier (ASID) and a privilege level bit in storage of the hardware processor core;
• and
• predicting, by a branch predictor of the hardware processor core, a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the storage;
• and
• fetching, by the instruction fetch circuit, the target instruction.

An apparatus comprising:

• an instruction fetch circuit to fetch instructions;
• storage for a data structure comprising a plurality of entries that each include an address space identifier (ASID) and a privilege level bit;
• and
• a branch predictor, coupled to the instruction fetch circuit and the storage, to:
• for a match in the storage of a current instruction pointer for a branch instruction to an entry of the plurality of entries in the storage, predict a target instruction corresponding to the branch instruction and cause the target instruction to be fetched by the instruction fetch circuit and,
• for no match in the storage of the current instruction pointer to the plurality of entries in the storage, cause a next sequential instruction pointer from the current instruction pointer to be fetched by the instruction fetch circuit.