US 2025/0053641 A1 · PROCESSOR EXTENSIONS TO PROTECT STACKS DURING RING TRANSITIONS

Abstract

A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

Claims20

Dependent claims

A processor comprising:

a first register corresponding to a first privilege level, the first register to store a first shadow stack pointer (SSP), the first SSP to identify a first shadow stack to be used by the processor at the first privilege level;
a second register corresponding to a second privilege level different than the first privilege level, the second register to store a second SSP, the second SSP to identify a second shadow stack to be used by the processor at the second privilege level;
and
a processor core circuitry, operatively coupled to the first and second registers, to:
receive an instruction to change the first privilege level associated with a currently active application to the second privilege level;
select, in view of the second privilege level, the second SSP stored in the second register;
and
identify, using the second SSP, the second shadow stack for use at the second privilege level.

5 more elements

A method comprising:

storing a first shadow stack pointer (SSP) in a first register corresponding to a first privilege level, the first SSP identifying a first shadow stack used at the first privilege level;
storing a second SSP in a second register corresponding to a second privilege level different than the first privilege level, the second SSP identifying a second shadow stack used at the second privilege level;
receiving an instruction to change the first privilege level associated with a currently active application to the second privilege level;
selecting, in view of the second privilege level, the second SSP stored in the second register;
and
identifying, using the second SSP, the second shadow stack for use at the second privilege level.

3 more elements

A system comprising:

a system memory;
and
a processor coupled with the system memory, the processor comprising:
a first register corresponding to a first privilege level, the first register to store a first shadow stack pointer (SSP), the first SSP to identify a first shadow stack to be used by the processor at the first privilege level;
a second register corresponding to a second privilege level different than the first privilege level, the second register to store a second SSP, the second SSP to identify a second shadow stack to be used by the processor at the second privilege level;
and
a processor core circuitry, operatively coupled to the first and second registers, to:
receive an instruction to change the first privilege level associated with a currently active application to the second privilege level;
select, in view of the second privilege level, the second SSP stored in the second register;
and
identify, using the second SSP, the second shadow stack for use at the second privilege level.

8 more elements

Dependencies are inferred from the claim text.

Processor extensions to protect stacks during ring transitions

Life of this patent

Processor extensions to protect stacks during ring transitions

Life of this patent

Abstract

Claims20