Input/output expander register addressing

An apparatus, comprising:

• a controller;
• a plurality of memory dice;
• and
• a memory device interface to transfer communication between the controller and the plurality of memory dice, wherein the memory device interface comprises:
• a feature register comprising a first feature register portion and a second feature register portion, wherein the first feature register portion and the second feature register portion are designated to circuitry associated to a single output channel;
• a decoder coupled to a first input of the first feature register portion and a second input of the second feature register portion;
• and
• an address decode bit written to the first feature register portion to designate a selection between the first feature register portion and the second feature register portion when receiving signals from the decoder.

A system comprising:

• a memory sub-system comprising a non-volatile memory device;
• and
• a processing device coupled to the memory sub-system by a memory device interface, the memory device interface comprising:
• a feature register comprising a first plurality of designated feature register portions designated to circuitry associated with a first set of output channels and a second plurality of designated feature register portions designated to a circuitry associated with a second set of output channels;
• a first decoder coupled to a first input of the first plurality of designated feature register portions;
• a second decoder coupled to a second input of the second plurality of designated feature register portions;
• a multiplexor coupled to an input of the second decoder;
• and
• a third decoder coupled to an input of the first decoder and an input of the multiplexor.