US 2025/0053524 A1 · Clock Generation for Timing Communications with Ranks of Memory Devices

Abstract

A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Claims21

Dependent claims

(canceled)

A memory controller to control the operation of a first memory device and a second memory device, the memory controller comprising:

a timing circuit, including:
a first storage element to store a first calibration value used to control timing for receiving data from the first memory device, and a second storage element to store a second calibration value used to control writing data to the first memory device;
and
a third storage element to store a third calibration value used to control timing for receiving data from the second memory device, and a fourth storage element to store a fourth calibration value used to control writing data to the second memory device;
a sampling circuit, coupled to the timing circuit, to receive data from the first memory device based on the first calibration value and from the second memory device based on the third calibration value;
and
a transmitter, coupled to the timing circuit, to write data to the first memory device based on the second calibration value and to write data to the second memory device based on the fourth calibration value.

4 more elements

A method of controlling the operation of a first memory device and a second memory device, comprising, at a memory controller:

storing in a first storage element of the memory controller a first calibration value used to control timing for receiving data from the first memory device, and storing in a second storage element of the memory controller a second calibration value used to control writing data to the first memory device;
and
storing in a third storage element of the memory controller a third calibration value used to control timing for receiving data from the second memory device, and storing in a fourth storage element of the memory controller a fourth calibration value used to control writing data to the second memory device;
receiving data from the first memory device, using a sampling circuit, based on the first calibration value and receiving data from the second memory device, using the sampling circuit, based on the third calibration value;
and
transmitting write data to the first memory device, using a transmitter, based on the second calibration value and transmitting write data to the second memory device, using the transmitter, based on the fourth calibration value.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/807,548Filed 16 Aug 2024

Priority

29 Nov 2010

Published

13 Feb 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 13/1689
Details of memory controller: synchronisation and timing concerns
G06F 1/04
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00: generating or distributing clock signals or signals derived directly therefrom
G06F 1/06
Generating or distributing clock signals or signals derived directly therefrom: clock generators producing several clock signals
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency

Family

Application61/417,845Us provisional application · filed 29 Nov 2010

Application13/990,370Continuation · filed 29 May 2013

Application14/954,940Continuation · filed 30 Nov 2015

Application15/424,714Continuation · filed 3 Feb 2017

Application16/228,695Continuation · filed 20 Dec 2018

Application16/921,061Continuation · filed 6 Jul 2020

Application18/135,095Continuation · filed 14 Apr 2023

Application18/807,548Continuation

US 10,162,772 B2Related patent

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US 12,066,958 B2Related patent

US 2013/0254585 A1Published application

US 2016/0116938 A1Published application

US 2017/0192912 A1Published application

US 2019/0196992 A1Published application

US 2021/0049118 A1Published application

US 2023/0359572 A1Published application

US 9,201,444 B2Related patent

US 9,563,228 B2Related patent

US 2025/0053524 A1This patent

From the US filing history. Foreign family members aren’t listed.

Abstract

Claims21

Dependent claims

(canceled)

A memory controller to control the operation of a first memory device and a second memory device, the memory controller comprising:

a timing circuit, including:
a first storage element to store a first calibration value used to control timing for receiving data from the first memory device, and a second storage element to store a second calibration value used to control writing data to the first memory device;
and
a third storage element to store a third calibration value used to control timing for receiving data from the second memory device, and a fourth storage element to store a fourth calibration value used to control writing data to the second memory device;
a sampling circuit, coupled to the timing circuit, to receive data from the first memory device based on the first calibration value and from the second memory device based on the third calibration value;
and
a transmitter, coupled to the timing circuit, to write data to the first memory device based on the second calibration value and to write data to the second memory device based on the fourth calibration value.

4 more elements

A method of controlling the operation of a first memory device and a second memory device, comprising, at a memory controller:

storing in a first storage element of the memory controller a first calibration value used to control timing for receiving data from the first memory device, and storing in a second storage element of the memory controller a second calibration value used to control writing data to the first memory device;
and
storing in a third storage element of the memory controller a third calibration value used to control timing for receiving data from the second memory device, and storing in a fourth storage element of the memory controller a fourth calibration value used to control writing data to the second memory device;
receiving data from the first memory device, using a sampling circuit, based on the first calibration value and receiving data from the second memory device, using the sampling circuit, based on the third calibration value;
and
transmitting write data to the first memory device, using a transmitter, based on the second calibration value and transmitting write data to the second memory device, using the transmitter, based on the fourth calibration value.

3 more elements

Dependencies are inferred from the claim text.

Clock Generation for Timing Communications with Ranks of Memory Devices

Life of this patent

Abstract

Claims21

Clock Generation for Timing Communications with Ranks of Memory Devices

Life of this patent

Abstract

Claims21