Duplication of tensors for memory allocation in a reconfigurable data processor

A data processing system comprising:

• an array of reconfigurable units including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs), each of the plurality of the PMUs further comprising a memory having one or more read I/O ports and one or more write I/O ports,
• a compiler configured to receive a tensor including ‘n’ (one or more) memory access patterns of a first type (read) and ‘m’ (one or more) memory access patterns of a second type (write) located in a logical memory of the compiler, each memory access pattern of the first type (read) including a first type (read) of memory access (read context) and each memory access pattern of the second type (write) including a second type (write) of memory access (write context), wherein
• the compiler is further configured to create a plurality of copies of the tensor to create a plurality of duplicate tensors,
• assign, up to ‘n’ (one or more) first type of contexts and up to ‘m’ (one or more) of the second type of contexts to one or more duplicate tensors, such that such that no duplicate of the tensor has more contexts of a particular type than ports of that type,
• trim a duplicate tensor to retain portions including its corresponding assigned contexts and remove portions that are inconsequential to the assigned contexts, and
• dispatch the assigned contexts in the duplicate tensor to one or more of the plurality of the PMUs.

A system comprising:

• an array of reconfigurable units including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs), each of the plurality of the PMUs further comprising a memory having one or more first type of (read) I/O ports and one or more second type of (write) I/O ports,
• a compiler configured to receive a tensor including a plurality of memory access patterns (contexts,) each memory access pattern further including one or more memory accesses (data regions),
• wherein the compiler is further configured to:
• determine a total number of memory access patterns in the tensor,
• determine a type of each memory access pattern,
• determine a critical group of memory access patterns including critical contexts,
• determine one or more non-critical groups of memory access patterns including non-critical contexts,
• create n copies of the tensor to create n duplicate tensors wherein n is equal to the number of access patterns in the critical group,
• create an initial assignment schedule with n duplicate tensors by:
• assigning the critical contexts to the n duplicate tensors,
• assigning a 1st set of non-critical contexts to the n duplicate tensors, and
• assigning a 2nd set of non-critical contexts to the n duplicate tensors,
• create a final assignment schedule by:
• retaining the 1st set of non-critical contexts in the n duplicate tensors,
• assigning to x additional duplicate tensors, x contexts from the 2nd set of non-critical contexts which are colliding with the 1st set, and
• extending the critical contexts to the x additional duplicate tensors;
• dispatch all the contexts as per the final assignment schedule to the n and the x duplicate tensors such that no duplicate tensor has more contexts of a particular type than ports of that type,
• trim each duplicate tensor to retain portions including its corresponding assigned contexts and remove portions that are inconsequential to the assigned contexts;
• and
• provide the assigned contexts from the trimmed duplicates to a set of PMUs.