Memory control system and method

Abstract

A memory control system includes: a memory having a main storage module and a built-in EEPROM; a storage controller which, in a normal mode, reads a program in the main storage module on the basis of an instruction of a processor and performs read-write control on the built-in EEPROM, and in a test mode, performs read-write control on the main storage module or the built-in EEPROM on the basis of configuration of a test control signal, or completes a self-test on the basis of an instruction of the test control signal; and the processor. According to the present disclosure, resource consumption is greatly reduced; logic of a hardware control reading part after dormancy is omitted and the time consumed during dormancy and wake-up is reduced; and only one counter and one time sequence control unit are used to implement control of the time sequence of the whole system.

Dependencies are inferred from the claim text.