Private memory mode sequential memory access in multi-threaded computing

A processor, comprising:

• a sequencer;
• a memory port coupled to the sequencer, wherein the sequencer is configured to send thread block dimension information and addressing parameters stored in scalar registers of the sequencer to the memory port, and the memory port is configured to generate, based on the thread block dimension information and the addressing parameters, a scalar memory address pointing to a storage location of a piece of data for the first thread of a warp;
• and
• a memory unit coupled to the memory port via a memory interface and configured to load K words of data for the warp to a vector register from K consecutive memory addresses starting at the scalar memory address for a data loading process or store K words of data for the warp from the vector register to the K consecutive memory addresses starting at the scalar memory address for a data storing process, K being a warp size representing a number of threads to be concurrently processed by executing a vector instruction, wherein the piece of data has a size less than or equal to a word size.

A method, comprising:

• sending, by a sequencer to a memory port, thread block dimension information and addressing parameters stored in scalar registers of the sequencer;
• generating, by the memory port and based on the thread block dimension information and the addressing parameters, a scalar memory address pointing to a storage location of a piece of data for a first thread of a warp;
• and
• storing, by a memory interface and a memory unit, K words of data for the warp from a vector register to K consecutive memory addresses starting at the scalar memory address, K being a warp size representing a number of threads to be concurrently processed by executing a vector instruction, wherein the piece of data has a size less than or equal to a word size.