Extended error management with configurable header logs
AssigneeIntel Corporation
InventorsDiego Garcia Rodriguez, Omar Avelar Suarez, Claudia Barajas Rivera, Gaurav Porwal, Luis Gonzalez Perez
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Abstract
An example of an apparatus may include a processor to process request transactions and completion transactions for one or more respective communication protocols, memory coupled to the processor to store error-related transaction information, and circuitry coupled to the memory to save the error-related transaction information in the memory for both the request transactions and the completion transactions for the one or more respective communication protocols. Other examples are disclosed and claimed.
Claims20
An apparatus, comprising:
- a processor to process request transactions and completion transactions for one or more respective communication protocols;
- memory coupled to the processor to store error-related transaction information;
- and
- circuitry coupled to the memory to save the error-related transaction information in the memory for both the request transactions and the completion transactions for the one or more respective communication protocols.
An apparatus, comprising:
- a processor to process request transactions and completion transactions for one or more respective communication protocols;
- memory coupled to the processor to store error-related transaction information;
- and
- circuitry coupled to the memory to save the error-related transaction information in the memory associated with two or more error severity levels for the one or more respective communication protocols.
An electronic device, comprising:
- a processor;
- interface circuitry coupled to the processor to support one or more communication protocols;
- and
- error management circuitry to collect header log information from both request transactions and completion transactions for the one or more communication protocols.
Dependencies are inferred from the claim text.