Deadlock-free scheduling of a task graph on a multi-core processor
AssigneeSnap Inc.
InventorsCornelis Hermanus Van Berkel, Lennart Bamberg, Luc Johannes Wilhelmus Waejien
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AssigneeSnap Inc.
InventorsCornelis Hermanus Van Berkel, Lennart Bamberg, Luc Johannes Wilhelmus Waejien
Estimating the term…
Examples in the present disclosure relate to the mapping of a task graph specifying a neural network on a multi-core processor. The multi-core processor exchanges messages in a message exchange network on chip (NoC). The task graph has a plurality of nodes interconnected by directed edges. For each node, a priority is assigned to the node and the node is assigned to a particular processor core of the multi-core processor. For each directed edge, a priority is assigned to the directed edge and the directed edge is assigned to an acyclic NoC path. The priority assigned to each node is a highest one of one or more priorities assigned to one or more of the directed edges that are incoming edges of the node. The priority assigned to each directed edge of the directed edges exceeds the priority of the node from which the directed edge is outgoing.
A method for mapping a task graph specifying a neural network for execution by a multi-core processor, the task graph comprising a plurality of nodes interconnected by directed edges, each node of the plurality of nodes representing at least one computational task to be performed in executing the neural network, each directed edge of the directed edges directed from a source node of the plurality of nodes to a destination node of the plurality of nodes representing a dependency of the at least one computational task represented by the destination node on one or more event messages from the at least one computational task represented by the source node, the multi-core processor comprising a plurality of processor cores to exchange messages in a message exchange network on chip (NoC), the method comprising:
(canceled)
A multi-core processor comprising a plurality of processor cores to exchange messages in a message exchange network on chip (NoC) and to execute a neural network specified by a task graph, the task graph comprising a plurality of nodes interconnected by directed edges, each node of the plurality of nodes representing at least one computational task to be performed in executing the neural network, each directed edge of the directed edges directed from a source node of the plurality of nodes to a destination node of the plurality of nodes representing a dependency of the at least one computational task represented by the destination node on one or more event messages from the at least one computational task represented by the source node, the task graph being mapped on the multi-core processor by operations comprising:
Dependencies are inferred from the claim text.