Compilation for synchronous processor

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for compiling latency insensitive programs for a synchronous processor. One of the methods includes receiving an intermediate representation of a program specifying operations to be performed by a plurality of respective components of a synchronous processor, wherein the intermediate representation assigns, to each operation of the plurality of operations, a respective clock cycle value at which the operation is scheduled to be executed by the synchronous processor. The intermediate representation is processed to generate a respective update window for each operation in the intermediate representation requiring a hardware configuration update, wherein the update window specifies a time range during which a configuration update instruction can be executed to effectuate the hardware configuration update. Configuration update instructions are scheduled to occur during one or more update windows and according to the configuration constraints of the synchronous processor.

Dependencies are inferred from the claim text.