Execution Circuitry for Floating-Point Power Operation

An apparatus, comprising:

• execution pipeline circuitry configured to perform multiple categories of floating-point instructions, that operate on one or more inputs in a first floating-point format to generate an output in the first floating-point format, including:
• a power function instruction that specifies both a base input and a power input, a base-2 logarithm instruction, and a base-2 power instruction, wherein the execution pipeline circuitry includes:
• a first pipeline portion having one or more stages that includes base-2 logarithm circuitry configured to evaluate the base-2 logarithm of a first input to determine a first result in a second floating-point format having a greater number of bits than the first floating-point format;
• a second pipeline portion configured to:
• receive the first result from the base-2 logarithm circuitry;
• and
• multiply, by multiplication circuitry, the received first result by a second input to generate a multiplication result;
• a third pipeline portion configured to:
• receive the multiplication result from the multiplication circuitry;
• and
• evaluate, by base-2 power function circuitry, two to the power of a representation of the multiplication result to generate an instruction result in the first floating-point format;
• and
• control circuitry configured to:
• control multiplexer circuitry to select the first result from the first pipeline portion as a result of a base-2 logarithm instruction;
• and
• control multiplexer circuitry to bypass the first pipeline portion and provide, as an input to the second pipeline portion, a power input provided by a base-2 power instruction.

A method, comprising:

• controlling execution pipeline circuitry to perform multiple categories of floating-point instructions, that operate on one or more inputs in a first floating-point format to generate an output in the first floating-point format, including:
• a power function instruction that specifies both a base input and a power input, a base-2 logarithm instruction, and a base-2 power instruction, wherein the execution pipeline circuitry includes:
• a first pipeline portion having one or more stages that includes base-2 logarithm circuitry configured to evaluate the base-2 logarithm of a first input to determine a first result in a second floating-point format having a greater number of bits than the first floating-point format;
• a second pipeline portion configured to:
• receive the first result from the base-2 logarithm circuitry;
• and
• multiply, by multiplication circuitry, the received first result by a second input to generate a multiplication result;
• and
• a third pipeline portion configured to:
• receive the multiplication result from the multiplication circuitry;
• and
• evaluate, by base-2 power function circuitry, two to the power of a representation of the multiplication result to generate an instruction result in the first floating-point format;
• and
• wherein the controlling includes:
• utilizing the first, second, and third pipeline portion for a power function instruction;
• controlling multiplexer circuitry to select the first result from the first pipeline portion as a result of a base-2 logarithm instruction;
• and
• controlling multiplexer circuitry to bypass the first pipeline portion and provide, as an input to the second pipeline portion, a power input provided by a base-2 power instruction.

An apparatus, comprising:

• decode circuitry configured to decode a floating-point power instruction that specifies, in a first floating-point format, a first input and a second input;
• and
• execution pipeline circuitry configured to, for execution of the floating-point power instruction, operate on the first and second inputs to generate a result in the first floating-point format, wherein the execution pipeline circuitry includes:
• a first pipeline portion having one or more stages that includes base-2 logarithm circuitry configured to evaluate the base-2 logarithm of the first input to determine a first result in a second floating-point format having a greater number of bits than the first floating-point format;
• a second pipeline portion configured to:
• receive the first result from the base-2 logarithm circuitry;
• and
• multiply, by multiplication circuitry, the received first result by the second input to generate a multiplication result using head-tail arithmetic with head and tail portions that have fewer bits than a number of bits of the second floating-point format;
• and
• a third pipeline portion configured to:
• receive the multiplication result from the multiplication circuitry;
• and
• evaluate, by base-2 power function circuitry, two to the power of a representation of the multiplication result to generate a result of the floating-point power instruction in the first floating-point format.