Memory device and computing system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorYeonjin Lee
Life of this patent
Estimating the term…
Abstract
A memory device configured to connect to a plurality of hosts through an interconnect device and to communicate with the plurality of hosts by a compute express link (CXL) protocol includes a command scheduler, a memory, and a priority scheduler. The command scheduler schedules commands included in requests from the plurality of hosts. The memory generates internal data by performing memory operations corresponding to the scheduled commands. The priority scheduler designates a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts and generates an output data by rearranging the internal data such that a data requested by the first host is output with priority.
Claims20
A memory device configured to connect to a plurality of hosts through an interconnect device and to communicate with the plurality of hosts by a compute express link (CXL) protocol, the memory device comprising:
- a command scheduler configured to schedule commands included in requests from the plurality of hosts;
- a memory configured to generate internal data by performing memory operations corresponding to the scheduled commands;
- and
- a priority scheduler configured to:
- designate a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts;
- and
- generate output data by rearranging the internal data such that a data requested by the first host is output with priority.
A computing system comprising:
- an interconnect device;
- a plurality of memory devices connected to the interconnect device;
- and
- a plurality of hosts connected to the interconnect device and configured to generate requests for access to the plurality of memory devices,
- wherein the plurality of memory devices are configured to communicate with the plurality of host by a compute express link (CXL) protocol, and
- wherein each of the plurality of memory devices includes:
- a command scheduler configured to schedule commands included in the requests from the plurality of hosts;
- a memory configured to generate internal data by performing memory operations corresponding to the scheduled commands;
- and
- a priority scheduler configured to designate a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts, and generate an output data by rearranging the internal data such that a data requested by the first host is output with priority.
A memory device configured to connect to a plurality of hosts through an interconnect device and to communicate with the plurality of hosts by a compute express link (CXL) protocol, the memory device comprising:
- a command scheduler configured to schedule commands included in requests from the plurality of hosts;
- a memory configured to generate internal data by performing memory operations corresponding to the scheduled commands;
- and
- a priority scheduler configured to:
- designate a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts;
- and
- generate an output data by rearranging the internal data such that a data requested by the first host is output with priority,
- wherein the priority scheduler includes:
- a host information register configured to store the attribute information of each of the plurality of hosts based on information in received packets;
- a priority mode selector configured to generate a priority mode signal based on the attribute information stored in the host information register;
- and
- an arbiter configured to generate the output data by rearranging the internal data in response to the priority mode signal.
Dependencies are inferred from the claim text.